1. Field of the Invention
This invention relates generally to active semiconductor devices, such as photonic, electronic or optoelectronic devices, and more particularly to photonic integrate circuits (PICs) that include active semiconductor devices, such as buried heterostructure active devices, such as Group III-V buried heterostructure semiconductor lasers, LEDs, modulators, photodiodes, heterojunction bipolar transistors, field effect transistors or other active devices for preventing current flow through designated regions of the device, such as high resistance current blocking layers on adjacent sides of the active region of such devices to provide for current confinement to the active region to enhance device efficiency.
2. Description of the Related Art
It is well known in the art to provide blocking layers for current confinement to the active region in buried heterostructure (BH) lasers or other such semiconductor active devices employed, for example, as an optical transmitter source, modulator or optical amplifier in optical telecommunication systems. Such a BH device employs junction blocking or reverse bias layers or blocking junctions, such as combinations of p-InP/n-InP layers. An example of such a blocking layer combination is disclosed in U.S. Pat. Nos. 4,470,143 and 5,148,439. However, due to intrinsic capacitance, these types of blocking junctions may not be readily adaptable for bit rates higher than 2.5 Gb/s. The particular problem with respect to these types of blocking layers is that the reverse biased p-n blocking junction possess a significant junction capacitance, limiting the high speed characteristics of such devices. Also, the reverse biased p-n junction in these devices may possess leakage paths leading to high thresholds in the case of laser diodes as well as low quantum efficiencies in all such devices.
Another type of blocking layer is made semi-insulating through the addition of one or combinations of Fe, Co, Ni, as a dopant, for example, in AlGaInAs, AlInAs, InP or InGaAsP. In particular, Fe is employed as a high resistance blocking layer such as disclosed in U.S. Pat. Nos. 4,660,208 and 4,888,624. Combination layers of Fe doped InP layers with p or n doped InP layers may be employed as illustrated in European Patent Application No. 0314372. As illustrated in these patents and publications, InP:Fe layers are utilized as blocking layers in BH lasers for current confinement to the active region of a semiconductor active device. Other Group III-V alloys, such as, for example, InGaAsP:Fe, may be employed as a blocking layer as illustrated in U.S. Pat. No. 6,028,875. The use of Fe doped Group III-V blocking layers is a well established current blocking technology but plagued by problems. In particular, Fe doped layers have poor stability so that Fe readily diffuses into adjacent semiconductor layers or materials, particularly the active region of a device. This diffusion process can occur more particularly during subsequent high temperature processing steps. European Patent Application No. 0208209 suggests a solution to this problem with the provision of an undoped spacer layer formed between the active region and adjacent layers and a second-growth InP:Fe, current blocking layer. Such a spacer layer prevents contamination of the active region by the impurity Fe in the adjacent, high resistive current blocking layer since the spacer layer functions as a diffusion inhibitor. Also, the spacer layer is made thin so that the leakage current outside of the buried active region is small. However, there is no mention in this publication of what the material might be for such a spacer layer.
A more recent approach for providing resistive layers to function as current blocking layers has been reported by S. Bouchoule et al. in an article entitled, “New Buried Heterostructure using MOVPE Selective Regrowth of Semi-Insulating (SI-) InAlAs for Low Capacitance Optical Sources”, Proceedings of The 14TH Annual Meeting of the IEEE Lasers & Electro-Optics Society (LEOS), La Jolla, San Diego, Calif., pp. 883–884, Nov. 14–15, 2001. SI-InAlAs layers were grown by MOVPE under growth conditions to obtain high resistivity with low capacitance and lattice matched to InP substrates. Under optimized conditions, a resistivity of 2×107 Ωcm was achieved. Similar results are reported in U.S. Pat. No. 5,679,603, in particular, in the discussion of embodiments 1–3 of that patent where the oxygen forms a deep donor level which is naturally taken into the crystal from residual oxygen and H2O in the MOCVD reactor and/or contamination of their source materials with oxygen utilized to growth Group III-V materials. Resistivity values of 5×104 Ωcm are indicated. However, for good quantum efficiencies with low current leakage, the resistivity required for the current blocking layer must be much higher than these values, preferably at least about 106 to 107 Ωcm or higher. U.S. Pat. No. 5,679,603 reports values in the range of a resistivity of 103 Ωcm to 108 Ωcm for InAlAs and indicates this to be a sufficiently high resistance compound semiconductor for current blocking layers. However, it would be desirable to obtain repeatable, maintained high resistivity values with even lower current leakage values in a narrow, upper resistivity range, e.g., about 106 to 108 Ωcm.
Generally, the resistivity for semi-insulating Group III-V or SI-III-V epitaxial growths can be achieved through background doping using low growth temperatures, such as below 550° C. As an example, in U.S. Pat. No. 5,804,840 to Ochi et al., high resistance or SI-InAlAs layers were achieved with growth temperatures of about 500° C. where background oxygen acts as a deep donor compensating the shallow acceptor, such as carbon, having a higher concentration than that of a shallow donor, such as background silicon. By controlling the relationship of deep and shallow donors and acceptors, a SI-layer, for example, of InAlAs, can be achieved. In this case, a resistivity “exceeding” 5×104 Ωcm was achieved, which is significantly lower than the desirability for a resistivity range of about 106 to 108 Ωcm or higher. The dependence on background doping levels in a reactor or other growth apparatus to achieve a desired level of resistivity is a difficult approach to form current blocking layers having uniform characteristics on continuous and repeatable fabrication basis. Background doping levels are a function of many variables, e.g., hydride source oxygen purity, metalorganic source purity, carrier gas purity, integrity of the vacuum seals in the MOCVD reactor, previously deposited materials within the confines of the MOCVD reactor chamber as well as on the susceptor, injector(s), etc. As a result, background doping levels can substantially vary from reactor run to reactor run, resulting in significant variations in the current blocking properties of the compounds and materials formed when utilizing this technique and approach.
U.S. Pat. No. 6,019,840 to Hartmann et al. does disclose SI-layers with resistances in the range of 109 Ωcm for SI-InGaP lattice-matched to GaAs. However, the greater need is for materials lattice-matched to InP for producing light emitting devices emitting and functioning at wavelengths (e.g., 1270 nm to 1650 nm) suitable for optical telecommunication applications, such as InAlAs latticed-matched to InP. As previously indicated relative to U.S. Pat. No. 5,804,840, SI-InAlAs, via low growth temperatures and background impurities, does not provide sufficiently high resistive values or well controlled active semiconductor devices employed particularly in optical telecommunication applications where the active semiconductor devices are integrated as a photonic integrated circuit (PIC) with close device spacing encountered so that the highest achievable levels of low current leakage in such devices are required, e.g., resistivities in a range of about 106 to 108 Ωcm or more.
Studies of higher resistivity materials of InAlP lattice-matched to GaAs and InAlAs lattice matched to InP suggested the possibility of achieving high resistance or semi-insulating materials through intentional oxygen doping, such as indicated in the paper of J. C. Chen et al., “Effects of Trimethylindium on the Purity of In0.5Al0.5P and In0.5Al0.5As Epilayers Grown by Metalorganic Chemical Vapor Deposition”, Journal of Electronic Materials, Vol. 6(4), pp. 362–365, 1997, although this paper was not directed to such intentional oxygen doping. The paper only relates to the study of background doping and impurities of carbon, silicon and oxygen. There has been increasing interest in intentional oxygen doping in MOCVD processing, as illustrated in the patent of U.S. Pat. No. 5,909,051 to Stockman et al., which teaches oxygen doping of p-type confinement layers (e.g. AlGaInP) in LEDs which improves device stability and, therefore, long term device reliability. Also in the case of AlGaInP lattice matched to GaAs, oxygen doping has been studied as indicated the paper of J. S. McCalmont et al., “The Effect of Oxygen Incorporation in Semi-Insulating (AlxGa1−x)yIn1−yP”, Journal of Applied Physics, Vol. 71(2), pp. 1046–1048, Jan. 15, 1992. In the case here, besides being lattice matched to GaAs, the source of oxygen was an O2 flow into the reactor and not from an oxygen source, such as diethyl aluminum ethoxide (DEALO), which has been found to compensate silicon donors due to oxygen-induced multiple deep levels in InGaAs:Si:O. See the article of J. W. Huang et al., “Controlled Oxygen Incorporation in Indium Gallium Arsenide and Indium Phosphide Grown by Metalorganic Vapor Phase Epitaxy”, Journal of Electronic Materials, Vol. 24(11), (7TH Biennial Workshop on Organmetallic Vapor Phase Epitaxy, Fort Myers, Fla., Apr. 2–5, 1995), pp. 1539–1546, November 1995. Also, previous mentioned U.S. Pat. No. 5,679,603 includes examples where the oxygen concentration in the crystal is controlled by the intentional doping of oxygen in AlInAs via an oxygen gas. However, in the embodiments reported, there is no indication of the resistivity levels except for the previously mentioned statement that high resistance semiconductor compounds fall in the range of 103 to 108 Ωcm. As indicated earlier, this large range is not acceptable for current blocking applications in demanding applications. Furthermore, using O2 as an oxygen source has the disadvantage of pre-reacting with the Group III-V growth source materials in the MOCVD reactor chamber. These pre-reactions make the controlled incorporation of oxygen difficult and cause other detrimental problems such as undesired deposits in the reactor chamber and problems with composition or constituent control of the epitaxial deposition of Group III-V components comprising the compounds or layers that are being epitaxially grown in the reactor.
Still another approach for forming semi-insulating blocking layers is to employ lateral oxidation techniques such as disclosed in U.S. Pat. Nos. 5,262,360 and 5,400,354 by exposing Al-containing layers to a wet oxidation process to form a native oxide in such layers or a diffusion process where oxide layer is formed on the surfaces to be oxidized and diffusion of water molecules or oxygen occurs from the oxide surface layer into the aluminum-containing layers to form its native oxide. A similar method may also be employed herein to produce the novel devices contemplated by this invention. In the utilization of this native oxide processing, the lateral oxidation to form the native oxide of the aluminum-containing layers can be controlled so as not enter the defined current flow region by utilizing Al-containing blocking layers containing a higher Al mole fraction than the Al mole fraction of any of the layers formed in the current flow region so that the lateral oxidation can be easily terminated at the lower mole fraction Al-containing layers in the current flow region as taught in U.S. Pat. No. 6,201,264, or by forming a mesa or groove current confinement region where the Al-containing layers are stepped so that the oxidation extends only to layer step region as taught in U.S. Pat. No. 6,287,884. Both of these patents are incorporated herein by their reference.